1. Field of the Invention
This invention relates to RF and microwave amplifiers in general and more particularly to Darlington gain block amplifiers that have improved biasing to prevent potentially damaging conditions from occurring. The invention also prevents a voltage pulse on the output of the amplifier that is formed during the start-up process, which can damage the circuitry connected to the output of the gain block amplifier.
2. Description of Related Art
Darlington gain block amplifiers are widely used in RF and microwave systems. Darlington amplifiers have a frequency range that starts at DC. The biasing conditions needed by the transistors require de-coupling capacitors at the input and output. The de-coupling capacitors determine the low end of the amplifier frequency range. Normally, Darlington gain block amplifiers receive a DC bias voltage from an ideal current source. In practice, the current source is replaced by a voltage source with a series resistor, which converts it to a reasonably good current source. The resistor value typically ranges up to a few hundred ohms. Therefore, the DC voltage from the voltage source can be up to 10 to 15 volts. An optional choke can be connected in series with the resistor to increase the total impedance at the high end of the amplifier frequency range to minimize gain and power loss.
Referring to FIG. 1, a typical Darlington gain block amplifier 12 and biasing configuration is shown. A pair of NPN transistors Q1 and Q2, are connected in a Darlington configuration. Transistor Q1 has a base QB1, an emitter QE1 and a collector QC1. Transistor Q2 has a base QB2, an emitter QE2 and a collector QC2. The emitter QE1 is connected to base QB2. The collectors QC1 and QC2 are connected together. A biasing network 14 is connected to the amplifier. Biasing network 14 supplies the proper biasing voltages to transistors Q1 and Q2. Resistor R1 is connected between base QB1 and collector QC1. Resistor R2 is connected between base QB1 and ground. Resistor R3 is connected between emitter QE1 and ground. Resistor R4 is connected between emitter QE2 and ground. A 50 ohm resistor R5 and input de-coupling capacitor C1 are serially connected between base QB1 and ground. 50 ohm resistor R6 and output de-coupling capacitor C2 are serially connected between the collectors QC1, QC2 and ground. A controlled current source P1 is connected to the collector QC1, QC2 junction. The input to the amplifier is on the base QB1. The output from the amplifier is taken from the collector QC2.
If a low frequency response is desired, the de-coupling capacitors C1 and C2 can have a significant value. For example, for a frequency of 100 KHz, the de-coupling capacitors would have a value around 0.2 μF or more. Where the input and output impedances are equal to a value of 50 ohms, the input and output de-coupling capacitors normally have the same value.
Unfortunately, an initial start-up process can result in a dangerous ‘voltage bump’ or overshoot voltage occurring on the transistors of the Darlington amplifier. In addition to the danger of damaging the Darlington amplifier, the voltage bump can overload and possibly damage the circuitry connected to the output of the Darlington amplifier. The transient process when the current source has a sharp ramp (small rise time) will be detailed next. The worst case is when the current source P1 goes from zero to the nominal current value instantaneously. This would occur if the current source was manually connected such as by plugging in a connector or by turning on a mechanical switch. Initially, the de-coupling capacitors C1 and C2 are not charged and transistors Q1 and Q2 are not conducting.
The initial response of the circuit of FIG. 1 can be analyzed by using an example of a simplified circuit. Turning to FIG. 2, a simplified circuit 20 of FIG. 1 is shown. All the component values in FIG. 2 are typical values for a Darlington amplifier. FIG. 2 has two current probes 11 and 12, current source P1, 510 ohm resistor R1, 580 ohm resistor R2, 50 ohm resistor R5, 50 ohm resistor R6 and 0.2 μF capacitors C1 and C2. Current source P1 has a rise time of 100 nanoseconds. The circuit of FIG. 2 was analyzed using Agilent ADS 2001 circuit simulator software. When the current source is turned on, capacitors C1 and C2 will begin to charge. However, capacitors C1 and C2 will charge at a differing rate due to the difference in time constants because series resistors R1+R5 and R6 are different. The total current will be split into two unequal parts, initially in a proportion to approximately (R1+R5)/R6.
FIGS. 3 and 4 show the voltage versus time for the simplified circuit 20 of FIG. 2 at nodes ‘DC out’ and ‘base’, respectively. FIG. 5 shows current versus time for circuit 20 at probes I1 and I2. As seen in FIG. 5, the current I1 charging C1 is about 10 times less than the current charging C2. During charging, the current source split ratio will change because a larger portion of the current will sink through R1 and R2 directly to ground. After more than 1 millisecond, C2 will be charged and its charge current I2 will drop to almost zero in FIG. 5. At this point, input capacitor C1 will also be charged and all of the 17 milliamps of current will sink through resistors R1 and R2. The total voltage drop across resistors R1 and R2 is 18.5 volts as seen in FIG. 3 and this is equivalent to the maximum voltage on node ‘DC out’. The voltage drop across resistor R2 is 9.9 volts as seen in FIG. 4. This voltage is equivalent to the maximum voltage on the node ‘base’ of transistor Q1 of circuit 20.
When transistors Q1 and Q2 are added to the simulated circuit, they will start to conduct when the voltage across R2 reaches 2.6 to 2.8 volts. This is twice the base to emitter voltage drop (Vbe) for an indium phosphide heterojunction bi-polar transistor (InP HBT). Transistor Q1 starts to conduct when the node base voltage reaches approximately 1.3 to 1.4 volts. At this point, the current sinking through transistor Q1 will not be high. Transistor Q2 starts to conduct when the node base voltage reaches approximately 2.6 to 2.8 volts and sinks most of the current. At the time that transistor Q2 starts to conduct, the device voltage will already be 7 volts. Therefore, when transistor Q2 first starts to conduct it will be subjected to the 7 volts peak voltage. Note that the total peak current through the amplifier of FIG. 8 exceeds the nominal current source value of 17 ma because the discharging current of output capacitor C2. If the transistors survive the overvoltage and discharge current conditions, they will shunt the current until the device voltage drops to a steady value of 5 volts. This is shown in FIGS. 6-9. FIG. 6 shows the total device voltage at node ‘DC out’ versus time.
FIG. 7 shows the amplifier input voltage or the base voltage of input transistor Q1 versus time.
FIG. 8 shows the total device current versus time, which includes the current from the current source and the discharge current from output capacitor C2. This can be more than the total current source current.
FIG. 9 shows the emitter currents through transistors Q1 and Q2 versus time.
The most dangerous moment for the transistors is when the total device voltage reaches a maximum value (marker M5 in FIG. 6) and transistor Q2 starts to conduct (marker M4 in FIG. 9). The total device voltage is about 6.85 volts at this moment.
FIGS. 10-13 show actual oscilloscope measurements on a circuit of FIG. 1 that was built. A Keithley 236 power supply was used for the current source. An Infiniium HP 54035A oscilloscope from Agilent was used to measure the voltage versus time for various current source values. FIG. 10 shows the output voltage versus time for a current source of 11 milli-amps. FIG. 11 shows the output voltage versus time for a current source of 12 milli-amps. FIG. 12 shows the output voltage versus time for a current source of 13 milli-amps. FIG. 13 shows the output voltage versus time for a current source of 14 milli-amps.
FIGS. 10-13 show how quickly the amplifier peak voltage rises with an increase in the current source value. As seen in FIG. 13, permanent damage to the output transistors of the amplifier occurred with a current source value of 14 milli-amps. The amplifier device voltage does not come to a steady 5 volt value. Sequential gain measurements confirm that the amplifier is permanently damaged.
This problem only exists for a current source with small rise times. For a slow current source, the charging rate of the input capacitor C1 and output capacitor C2 are about the same and determined mostly by the long rise time of the current source. Therefore the output voltage will not have the peaking shape and the voltage overshoot or voltage bump problem does not occur. With a slow current source, the amplifier can typically handle up to 51 milli-amps of current. Therefore, the overshoot problem is a pure transient issue at start up. It is not a steady state power dissipation limit problem.
While various Darlington transistor biasing schemes have previously been used, they have suffered from not being able to adequately protect against destructive transient voltage overshoot conditions and from interfering with normal amplifier operation. A current unmet need exists for an improved Darlington amplifier biasing circuit that is low in cost, protects against destructive transient voltage overshoot conditions and does not interfere with normal amplifier operation.